Logic based embedded dram technologiesMALLARDEAU, Catherine.Proceedings - Electrochemical Society. 2003, pp 133-135, issn 0161-6374, isbn 1-56677-376-8, 3 p.Conference Paper

Influence of bit line twisting on the faulty behavior of DRAMsAL-ARS, Zaid; HERZOG, Martin; SCHANSTRA, Ivo et al.IEEE International Workshop on Memory Technology, Design and Testing. 2004, pp 32-37, isbn 0-7695-2193-2, 1Vol, 6 p.Conference Paper

A 312MHz 16Mb random-cycle embedded DRAM macro with 73μW power-down mode for mobile applicationsMORISHITA, Fukashi; HAYASHI, Isamu; SHINKAWATA, Hiroki et al.IEEE International Solid-State Circuits Conference. 2004, pp 202-203, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

An 800MHz embedded DRAM with a concurrent refresh modeKIRIHATA, Toshiaki; PARRIES, Paul; WORDEMAN, Matt et al.IEEE International Solid-State Circuits Conference. 2004, pp 206-207, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

An experimental 256Mb non-volatile DRAM with cell plate boosted programming techniqueAHN, J-H; HONG, S-H; CHOI, J-H et al.IEEE International Solid-State Circuits Conference. 2004, pp 42-43, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 500MHz multi-banked compilable DRAM macro with direct write and programmable pipeliningBARTH, J; ANAND, D; DREIBELBIS, J et al.IEEE International Solid-State Circuits Conference. 2004, pp 204-205, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 0.6V 205MHz 19.5ns tRC 16Mb embedded DRAMHARDEE, K; JONES, F; TANIGUCHI, K et al.IEEE International Solid-State Circuits Conference. 2004, pp 200-201, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 1.6Gb/s/pin double-data-rale SDRAM with wave-pipelined CAS latency controlLEE, Sang-Bo; JANG, Seong-Jin; HEO, Hyoung-Jo et al.IEEE International Solid-State Circuits Conference. 2004, pp 210-211, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Scheduler-based DRAM energy managementDELALUZ, V; SIVASUBRAMANIAM, A; KANDEMIR, M et al.Design automation conference. 2002, pp 691-696, isbn 1-58113-461-4, 6 p.Conference Paper

On the design of hybrid DRAM/SRAM memory schemes for fast packet buffersGARCIA, Jorge; MARCH, Maribel; CERDA, Llorenc et al.Workshop on high performance switching and routing. 2004, pp 15-19, isbn 0-7803-8375-3, 1Vol, 5 p.Conference Paper

A 4Gb/s/pin 4-level simultaneous bidirectional 10 using a 500MHz clock for high-speed memoryKIM, Jin-Hyun; KIM, Su-A; KIM, Woo-Seop et al.IEEE International Solid-State Circuits Conference. 2004, pp 248-249, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

The effectiveness of scan test and its new variantsVAN DE GOOR, Ad J; HAMDIOUI, Said; AL-ARS, Zaid et al.IEEE International Workshop on Memory Technology, Design and Testing. 2004, pp 26-31, isbn 0-7695-2193-2, 1Vol, 6 p.Conference Paper

Future prospects of DRAM: emerging alternativesCHOI, Yoonsuk; LATIFI, Shahram.International journal of high performance systems architecture (Print). 2012, Vol 4, Num 1, pp 1-12, issn 1751-6528, 12 p.Article

Challenges of long term process stability and solutions for better controlCHOI, Jinphil; SEONG, Nakgeuon; LEE, Sangho et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7272, issn 0277-786X, isbn 978-0-8194-7525-1 0-8194-7525-4, 727234.1-727234.8, 2Conference Paper

Statistical approach to design DRAM bitcell considering overlay errorsPYO, Yu-Jin; KIM, Dae-Wook; PARK, Jai-Kyun et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7275, issn 0277-786X, isbn 978-0-8194-7528-2 0-8194-7528-9, 1Vol, 72751L.1-72751L.7Conference Paper

Exploring the limits of high temperature thermal processing for advanced 8-inch power technology manufacturingRUPP, T; DYROFF, N; SORSCHAG, K et al.IEEE / SEMI advanced semiconductor manufacturing conference. 2004, pp 27-31, isbn 0-7803-8312-5, 1Vol, 5 p.Conference Paper

Withdrawal of Fabrication and Properties of Pt/Bi_3.15Nd_0.85Ti₃O₁₂/HfO₂/Si Structure for Ferroelectric DRAM (FEDRAM) FETDAN XIE; YONGYUAN ZANG; YAFENG LUO et al.IEEE electron device letters. 2009, Vol 30, Num 10, issn 0741-3106, p. 1111Article

Memory controller optimizations for web serversRIXNER, Scott.IEEE/ACM international symposium on microarchitecture. 2004, pp 355-366, isbn 0-7695-2126-6, 1Vol, 12 p.Conference Paper

A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM applicationKIM, Kyu-Hyoun; LEE, Jung-Bae; LEE, Woo-Jin et al.IEEE International Solid-State Circuits Conference. 2004, pp 212-213, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Highly scalable sub-50nm vertical double gate trench DRAM cellSCHLOESSER, T; MANGER, D; KOWALSKI, B et al.International Electron Devices Meeting. 2004, pp 57-60, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

The 2007 Benjamin Franklin medal in electrical engineering presented to Robert H. Dennard, Ph.DDOBBINS, Lawrence W; KAPPS, Charles A.Journal of the Franklin Institute. 2011, Vol 348, Num 3, pp 459-475, issn 0016-0032, 17 p.Article

Overlay mark optimization using the KTD signal simulation systemMARCHELLI, Anat; GUTJAHR, Karsten; KUBIS, Michael et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7272, issn 0277-786X, isbn 978-0-8194-7525-1 0-8194-7525-4, 72722Y.1-72722Y.10, 2Conference Paper

Issues and Challenges of Double Patterning Lithography in DRAMKIM, Seo-Min; KOO, Sun-Young; CHOI, Jae-Seung et al.Proceedings of SPIE, the International Society for Optical Engineering. 2007, pp 65200H.1-65200H.7, issn 0277-786X, isbn 978-0-8194-6639-6Conference Paper

Energy-efficient value-based selective refresh for embedded DRAMsPATEL, K; BENINI, L; MACII, Enrico et al.Lecture notes in computer science. 2005, pp 466-476, issn 0302-9743, isbn 3-540-29013-3, 11 p.Conference Paper

A 3.6Gb/s/pin simultaneous bidirectional (SBD) I/O interface for high-speed DRAMKIM, Jae-Kwan; CHOI, Jung-Hwan; SHIN, Sung-Woo et al.IEEE International Solid-State Circuits Conference. 2004, pp 414-415, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper